Delay circuits are required in connection with a great variety of circuit applications. Accordingly, a great number of delay circuits are known which are designed for use with their respective operating conditions. A feature common to all delay circuits is that they supply, with a specific time delay at their output, an input signal they received. They differ according to the marginal operating conditions involved. These can be: the extent of the delay; varying setting range, the flexibility to receive all kinds of input signals; the circuitry technique or technology employed; etc.
Several clock pulses are frequently required for driving the numerous peripheral circuits such as decoder or selector circuits, flip-flops, etc. provided on a monolithically integrated FET storage chip. Supplying these several clock pulses from outside the chip places limitations on the number of chip connections, and results in pulse distortions or shifts on the supply lines. It is thus desirable not to supply all of these pulses to the chip from outside but to produce if possible all but on internally, i.e. on the respective chip. Thus, a chip internal clock driver has the general function of deriving from one single external clock pulse, or a clock pulse that already exists internally as the output signal of another driver, a second pulse which can drive--due e.g. to a large number of circuits to be driven (e.g. decoders)--a rather high load capacity (typical: 25 pF), and which is delayed with respect to the input signal by a predetermined time t.sub.d.
It is known in that connection that in the least complicated case each FET switching stage, e.g. inverter, shows a delay. Delays on a given circuit field are therefore always achieved in that a capacitor or a capacitive component is charged or discharged via an FET or a comparable circuit element. It is also known that clock drivers with a non-inverted output can be realized by a series arrangement of two or, generally, an even number of standard inverters. As a typical value for the overall delay time t.sub.d of a two stage inverter series with field effect transistors approximately 10 ns can be assumed.
Since the delay circuits of the type discussed herein are based on the discharge of a capacitive element it would appear possible to obtain longer delay times by means of an increase of the effective capacitance value. However, there is the conflicting factor that with semiconductor circuits provided for monolithic integration this would have the direct consequence of increased area requirements which in turn is highly undesirable in most cases. If on the other hand the discharge current is reduced there appears the following problem: if while sensing a predetermined voltage level at the capacitive element, which voltage level determines the pulse delay, an FET or similar device is again used, its voltage is passed through very slowly, i.e. at a flat angle. This means, however, that this sensing circuit which advisably is identical with the output side inverter switches only slowly and thus can supply only a slow pulse rise to the circuits arranged in series to the delay circuit.